MOS capacitor

(PD) Image: John R. Brews
Cross section of MOS capacitor showing charge layers

MOS Capacitor

The MOS capacitor or metal-oxide semiconductor capacitor is a two terminal device consisting of three layers: a metal gate electrode, a separating insulator (often an oxide layer), and a semiconducting layer called the body. The device operates using the field effect, that is, the modulation of the surface conductivity of the semiconductor body by means of an applied voltage between the gate and the body.

Operation

(CC) Image: John R. Brews
Field effect: Top panels: An applied voltage bends bands, depleting holes from surface (left). The charge inducing the bending is balanced by a layer of negative acceptor-ion charge (right). Bottom panel: A larger applied voltage further depletes holes but conduction band lowers enough in energy to populate an inversion layer.

A device based upon a uniformly doped p-type body is described. The n-type case is similar. The device has four regions of operation depending upon the applied voltage between gate and body:

1. Accumulation: For a negative gate bias, holes are drawn to the semiconductor-insulator interface. A conducting surface extends from the bulk all the way to the interface, and the surface conductivity is enhanced by the accumulation of holes at the interface.
2. Flat bands: For a specific value of voltage, the bulk hole density is exactly the same from the bulk to the interface. The body is everywhere charge neutral because the hole density exactly balances the acceptor density. The flatband voltage corresponds to a zero potential drop in the body, but that does not necessarily correspond to zero applied voltage because of the contact potential between the metal gate and the body that leads to band bending even when zero voltage is applied.
3. Depletion: For a positive gate voltage, the holes are pushed away from the positive charge on the gate electrode, and a surface layer depleted of holes is formed extending from the interface to the depth necessary to make the exposed, immobile, negative acceptor ion charge exactly balance the positive charge on the gate. Increase in positive charge on the gate with increasing voltage is balanced by expansion of the depletion layer, increasing the acceptor charge.
4. Inversion: For positive gate voltages above a threshold voltage, a surface inversion layer of electrons forms in a narrow layer near the interface. This conducting inversion layer is separated form the p-type neutral bulk by the intervening insulating depletion layer of immobile acceptor charge. Once the gate voltage increases beyond the threshold voltage, additional positive charge on the gate is compensated by increased inversion layer electron charge, and the depletion layer depth no longer expands.

These various operation regions all are subsumed under the notion of the field effect, the modulation of conductivity by an applied electric field. The figure illustrates the charge balance for the cases of depletion (top panels) and inversion (bottom panels). On the left side of the figure, the band edges are plotted as a function of depth into the capacitor. The electron population of the bands depends upon how close they are to the Fermi level (the horizontal dashed line): because this separation varies with depth, so does the occupancy of the bands. For example, the valence bands are bent far below the Fermi level near the interface, so the energy levels in the valence band near the interface are filled with electrons, and there are no holes. At greater depth from the interface, however, the valence band edge becomes the bulk value, and is close enough to the Fermi level to allow some electron vacancies (holes, in other words) in the valence band. Consequently there are holes present in the bulk region, which are of a density equal to that of the negatively charged acceptor impurities in this region, resulting in a neutral bulk. The right panels in the figure illustrate the charge densities as a function of depth that are a consequence of the band bending.

Contact potential

The flat band condition is examined further here, to explain why a zero applied voltage does not necessarily imply flat bands. The metal gate contains electrons, as does the semiconductor body. For this discussion, the insulator is imagined as a charge-free inert layer. Suppose an electron is taken from the metal and transferred to the semiconductor. There are three possibilities: no work is done, some work is done to transfer the electron, or the electron provides energy during the transfer. In the first case, zero applied voltage corresponds to flat bands, but in the other two cases a short circuit between metal and semiconductor leads to a net transfer of electrons making the gate negatively charged in the first case and the semiconductor in the second case. That is, without any applied voltage, a charge transfer occurs, and this transfer results in a potential difference at zero applied voltage, the contact potential. Thus, to achieve flat bands (zero potential drop across the semiconductor), an applied voltage, the flatband voltage, is necessary.

The underlying cause of this charge transfer at a microscopic level is complicated in detail by the effects of interfaces including interface traps, and by charges in the insulating layer related to various defects. Within a few lattice spacings of an interface (≈1nm, say), the atomic arrangement differs from the bulk materials on either side of an interface, and the chemistry associated with such distortion can lead to charge dipoles (and related potentials) near this interface, even if the junction is free from defects. Two consequences are that the amount of charge transfer between the materials may depend upon the crystal orientation of the surfaces forming the interfaces, and it is not dictated entirely by the behavior of the metal and semiconductor idealized as bulk media. However, the driving force at an atomic level is the ability of some atoms to strip electrons from other atoms of a different species, a phenomenon called electronegativity of the atoms.

Admittance

(PD) Image: John R. Brews
Small-signal equivalent circuit of the MOS capacitor in inversion with a single trap level.

The MOS capacitor is often used as a test structure to monitor various fabrication steps in semiconductor processing. A key to these applications is the small-signal response of this device, that is, the current that flows in a circuit connecting this device to a small-amplitude gate voltage variation superposed upon a steady bias voltage. The ratio of the alternating current to the alternating voltage is the small-signal admittance of the device, and contained in this admittance is information about interface quality (traps, for example), insulator thickness, the distribution of dopants in the semiconductor body, and information on the defects in the semiconductor itself.

The basic ideas behind its use can be understood using the equivalent circuit in the figure. The circuit elements are:

The oxide capacitance C_OX

The depletion layer capacitance C_D

The inversion layer capacitance C_I

The trap capacitance C_T

The trap conductance for holes G_p

The trap conductance for electrons G_n

Based upon this circuit, the device small-signal admittance of only the semiconductor portion is given by:

$Y_{S}=j\omega C_{D}+{\frac {G_{p}\left(j\omega (C_{I}+C_{T})G_{n}+j\omega C_{I}\ j\omega C_{T}\right)}{j\omega (C_{I}+C_{T})G_{n}+j\omega C_{I}G_{p}+G_{n}G_{p}+j\omega C_{I}\ j\omega C_{T}}}\ .$

The device admittance must include the series oxide capacitance. This result can be simplified in various bias regimes. For example, the depletion mode of operation is used for investigating doping profiles, and depends essentially upon C_D. In depletion, C_I is negligible and:

$Y_{S}\approx j\omega \left(C_{D}+C_{T}{\frac {G_{p}}{j\omega C_{T}+G_{p}}}\right)\ ,$

which exhibits a time constant: at high frequencies, the trap term is negligible and at low frequencies Y_S is approximately C_D+C_T. On the other hand, when C_I is large,

$Y_{S}\approx j\omega \left(C_{D}+C_{I}{\frac {G_{p}\left(G_{n}+j\omega C_{T}\right)}{j\omega C_{I}\left(G_{n}+G_{p}+\ j\omega C_{T}\right)+G_{p}G_{n}}}\right)$ $=j\omega \left(C_{D}+C_{I}{\frac {G_{p}}{j\omega C_{I}+\left(j\omega C_{I}+G_{n}\right){\frac {G_{p}}{G_{n}+j\omega C_{T}}}}}\right)\ ,$

which also shows a frequency behavior: at low frequencies the inversion layer responds completely and Y_S is approximately C_D+C_I. At high frequencies, however, the inversion layer does not contribute and Y_S is approximately C_D alone.

The behavior of interface traps is most readily captured through the three trap components C_T, G_p, and G_n.

Greater detail follows next.

Depletion layer capacitance

In depletion, the inversion layer is unimportant, and C_I is not significant. The depletion layer capacitance can then be used to determine the distribution of dopant ions in the depletion layer, using two measurements of the MOS capacitance: one at high enough frequencies that the traps cannot respond, and one at low enough frequencies that they have an equilibrium response. By comparing these two measurements, the distortion due to the traps can be corrected, and the doping profile can be determined. The connection between the depletion layer capacitance and the doping profile is found intuitively from the requirement for charge neutrality: if the gate charge is increased an amount ΔQ, then (assuming no traps for the moment) the depletion width must expand to balance this charge. That is,

$\Delta Q=qN_{A}(w)\Delta w\ ,$

where w is the depletion width at the steady bias voltage, N_A(w) is the acceptor density at the depletion edge, and Δw is the incremental increase in the depletion width in response to ΔQ. It is easy to measure Δw because the depletion layer capacitance is simply the parallel plate capacitance of the depletion layer (we use per unit area values):

$C_{D}={\frac {\kappa _{S}\epsilon _{0}}{w}}\ ,$

where κ_S is the dielectric permittivity of the semiconductor. Thus, if we extract C_D from the measurement, the change in C_D under a small-signal change in bias dV is a direct measure of the doping concentration at the depletion edge N_A(w):

${\frac {d}{dV}}{\frac {1}{C_{D}}}={\frac {d}{dV}}{\frac {w}{\kappa _{S}\epsilon _{0}}}={\frac {1}{\kappa _{S}\epsilon _{0}}}{\frac {dw}{dV}}={\frac {1}{N_{A}(w)}}{\frac {1}{q\kappa _{S}\epsilon _{0}}}{\frac {dQ}{dV}}\ ,$

and it remains only to connect dQ/dV to the measured capacitance using the equivalent circuit. Assuming the traps do not play a role (or are corrected for):

${\frac {dQ}{dV}}={\frac {C_{OX}C_{D}}{C_{OX}+C_{D}}}\ .$

Further details are left to the general references.

Inversion layer capacitance

(PD) Image: John R. Brews
Three types of MOS capacitance vs. voltage curves. HF = high frequency, LF = low frequency, V_TH = threshold voltage and V_FB = flatband voltage

The figure shows three different types of small-signal capacitance vs. voltage curves observed in the MOS capacitor, in this case on a p-type substrate. A small-signal gate bias variation is superposed upon the steady bias V_G. For steady voltages V_G above the threshold voltage V_TH an inversion layer can form. The inversion regime of biases is divided in the figure into the strong inversion regime, where the inversion layer capacitance is so large at low frequencies that the overall capacitance is close to the insulator capacitance C_OX and the regime labeled simply "inversion", which is the regime where the inversion layer is gaining dominance over the depletion layer capacitance. These matters are explained further below.

The inversion layer becomes important for gate biases above the threshold voltage, and well below threshold the inversion layer capacitance is not important to the equivalent circuit. Also, in the MOS capacitor the inversion layer response to a small-signal change in gate bias is frequency dependent: an increase in gate bias demands a electrons to increase the population of the inversion layer. These electrons, however, are supplied by generation via traps in the depletion layer, and typically this generation is slow at temperatures up to room temperature. Thus, at high frequencies, the inversion layer will not respond, and the inversion layer capacitance is of minor importance in the equivalent circuit.

Thus, at low frequencies when the inversion layer fully responds to the small-signal gate bias, the low-frequency capacitance curve is:

${\frac {dQ}{dV}}={\frac {C_{OX}(C_{D}+C_{I})}{C_{OX}+C_{D}+C_{I}}}\ ,$

the so-called low-frequency CV curve, and when the small-signal gate bias is at a high frequency where the inversion layer does not respond at all:

${\frac {dQ}{dV}}={\frac {C_{OX}C_{D}}{C_{OX}+C_{D}}}\ ,$

the so-called high-frequency CV curve. The slow response of the inversion layer means that the steady bias must be changed slowly so the inversion layer has time to accommodate. If instead the steady bias is ramped up rapidly from flatbands to inversion, the inversion layer will not form, the depletion width will not be pinned but will continue to increase with the applied bias, and the small-signal capacitance will continue to follow the high-frequency CV curve (labeled "fast sweep" in the figure). The result is the so-called deep depletion CV curve.

Traps

The above description of CV curves incomplete until the voltage dependence of the capacitance is found. That is accomplished by determining how the band bending in the semiconductor is related to the applied bias. The charge in the device can be written:

$Q=Q_{SC}(\psi _{S})+Q_{T}(\psi _{S})\ ,$

where Q_SC is the semiconductor charge and Q_T is the trapped charge, both of which depend upon the band bending or potential drop ψ_S across the semiconductor, assuming the traps are at the interface. The total charge Q can be related to the field in the insulator, assuming no charge in the insulator, using Gauss's law:

$Q=\kappa _{OX}\varepsilon _{0}{\frac {V_{G}-\psi _{S}}{t_{OX}}}\ ,$

where κ_OX is the dielectric permittivity of the oxide (about 3.9 for SiO₂) and t_OX is the thickness.

A change in gate voltage then alters the charge on the device as:

$dQ=C_{OX}\left(dV_{G}-d\psi _{S}\right)=\left({\frac {dQ_{SC}}{d\psi _{S}}}+{\frac {dQ_{T}}{d\psi _{S}}}\right)d\psi _{S}=\left(C_{SC}+C_{T}\right)d\psi _{S}\ ,$

where C_T is the trap capacitance:

${\frac {dQ_{T}}{d\psi _{S}}}=C_{T}\ ,$

and C_SC is the semiconductor capacitance:

${\frac {dQ_{SC}}{d\psi _{S}}}=C_{SC}\ .$

Thus,

${\frac {d\psi _{S}}{dV_{G}}}={\frac {C_{OX}}{C_{OX}+C_{T}+C_{SC}}}\ .$

The function Q_SC can be calculated once the dopant distribution (the profile) is known, either by calculation or measurement. However, the trap charge is available only by measurement, as it depends on details of interface chemistry that are not well understood, and cannot be deduced from a theoretical model. It is clear that the trap charge in Q will alter the dependence of ψ_S upon V_G, resulting in a larger change of bias necessary for a given change in ψ_S ( a so-called interface trap stretch-out). At the same time, assuming a frequency small enough that the traps can respond, the device capacitance is affected by the traps:

${\frac {dQ}{dV_{G}}}={\frac {dQ}{dV_{G}}}={\frac {dQ}{d\psi _{S}}}{\frac {d\psi _{S}}{dV_{G}}}={\frac {C_{OX}\left(C_{SC}+C_{T}\right)}{C_{OX}+C_{SC}+C_{T}}}\ ,$

At high enough small-signal frequencies, the traps do not respond:

${\frac {dQ}{dV_{G}}}={\frac {C_{OX}C_{SC}}{C_{OX}+C_{SC}}}\ .$

A comparison of capacitance at a low and a high frequency therefore allows determination of the trap capacitance, and enables empirical correction of the measurements for stretch-out.

The traps themselves can be studied by careful extraction of the trap conductance parameters as a function of frequency. Such measurements have shown that MOS devices do not have just a single trap level, but a range of interface traps distributed in energy across the band gap and located close to the semiconductor-insulator interface. In carefully prepared Si-SiO₂ devices, the density of these traps may be as low as 10⁹ − 10¹⁰ /cm²·eV.

It may be noted that the MOS capacitor also can be used to study bulk traps in the semiconductor, and to study ion transport in the oxide layer (for example, the level of sodium contamination).